Systems & Design

Top Stories

I/O Design Challenges Grow In AI Data Centers And HPC Clu...
Physical I/Os can be a chokepoint for high-performance chips and high-speed interconnect protocols, requiring design tradeoffs and extra reliabilit...
Published on June 25th, 2026 by Liz Allan

Verification Methodologies Struggle To Keep Up With AI
Engineers are flooded with new capabilities. The problem now is how best to deploy them.
Published on June 25th, 2026 by Brian Bailey

Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?
Published on June 25th, 2026 by Ed Sperling

Designing Chips That Can Explain Themselves
On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior.
Published on June 17th, 2026 by Ann Mutschler

Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
Published on May 28th, 2026 by Liz Allan

Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Published on May 28th, 2026 by Ann Mutschler

Options Grow For Standardizing Data Movement And Sharing ...
But figuring out which ones to use, and when to use them, isn't always clear.
Published on May 20th, 2026 by Ed Sperling

Confusion Grows With More Interconnect Options And Tradeoffs
Each standard serves a specific use case, so chip architects are choosing more than one for a single design.
Published on May 18th, 2026 by Liz Allan

Using AI To Monitor Dashboards In Chips And Systems
AI agents can be used to identify potential issues during operation and react before it's too late.
Published on May 6th, 2026 by Ed Sperling

Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
Published on May 4th, 2026 by Ann Mutschler

More Top Stories »



Round Tables

Executive Outlook: Agentic AI’s Impact On Chip Design
Can engineers trust AI to get everything right in semiconductor design and verification?
Published on June 25th, 2026 by Ed Sperling

Designing Chips That Can Explain Themselves
On-die monitors, localized analytics, and lifecycle data are giving architects new ways to close the gap between design intent and silicon behavior.
Published on June 17th, 2026 by Ann Mutschler

Observability Is Essential For Modern Silicon
What on-die visibility reveals, and why it's especially important for AI, automotive, aerospace, and advanced packaging.
Published on May 28th, 2026 by Ann Mutschler

Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
Published on May 4th, 2026 by Ann Mutschler

AI Growing Impact On Chip Design And EDA Tools
Demand for faster design and more automation grows from key customers.
Published on April 15th, 2026 by Ed Sperling

More Roundtables »



Multimedia

How Far Left Can You Shift?
Complex chips require much more work earlier in the flow.
Published on June 24th, 2026 by Ed Sperling

Signoff Of Synthesis-Optimized Registers
When is a complex chip design ready to be shipped to manufacturing?
Published on June 17th, 2026 by Ed Sperling

Building Multi-Agent Systems For ASIC Flows
How agents can be used to divide and conquer IC design problems.
Published on June 10th, 2026 by Ed Sperling

The Evolution Of UCIe
How the standard matured from simple connectivity to secure data movement across multiple chiplets and packaging approaches.
Published on June 2nd, 2026 by Ed Sperling

Overcoming Bottlenecks In Data Movement
Where the choke points are in AI systems and what to do about them.
Published on May 27th, 2026 by Ed Sperling

More Multimedia »



See All Posts in System-Level Design »

Latest Blogs

Looking Past The Horizon

How Far Left Can We Really Shift Verification?
When verification is never fully complete, the only question left is how earl...
June 25, 2026
by Frank Schirrmeister
A System Perspective

Realizing The Future Of 3D-IC Design
Designing heterogeneously integrated packages necessitates a system-centric c...
June 25, 2026
by Keith Felton
NoC NoC

Reducing Avoidable Memory Trips In HBM Systems
Last-level cache helps manage data movement and reduces pressure on the exter...
June 25, 2026
by André Bonnardot
The Next Thread

Wafer-Scale vs. Chiplets: The New War? Part 2
Moving data fast enough so that compute stops waiting.
June 25, 2026
by Nandan Nayampally
Intelligent System Design

More Massive Still: Why AI Infrastructure Demands A Unifi...
Tokens-per-watt is now the primary metric driving AI data center optimization.
June 25, 2026
by Antti Lautanen
AI Agents In Design And Verification

Introducing An Agentic LLM For Chip Design
A fine-tuned model brings frontier-level AI performance to chip design.
June 25, 2026
by Tanay Biradar
First By Design

Scaling Production Test Without Scaling Complexity
Avoid synchronization and concurrency issues that commonly appear in multi-DU...
June 25, 2026
by Kwan Wee Lee
Making Formal Normal

Why Your NoC Verification Strategy Must Consider Using Fo...
Exhaustive proofs are the only way to find deep corner-case bugs that can res...
May 28, 2026
by Ashish Darbari
From Simulation To Always-On Physics

Foundation Model For Physics: The Next Layer Of Intellige...
Making validated physics reasoning continuously available across the engineer...
May 28, 2026
by John Bruggeman
Clock Talk

A Bench-To-In-Field Telemetry Platform For Data Center Po...
Enabling SoCs to run at their true power and performance limits across the fu...
May 28, 2026
by Aakash Jani

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
by Ed Sperling

Chip Industry Week In Review
AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
by The SE Staff

Chip Industry Week In Review
Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.
by The SE Staff

Toward Agentic Verification
Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
by Brian Bailey

Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
by Liz Allan

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