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Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.

AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.

Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon’s 1.5 micron L/S litho; IC market rises; Apple’s chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.

Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?

Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?