category: System-Level Design

category: Auto, Security & Edge AI

I/O Design Challenges Grow In AI Data Centers And HPC Clusters
By Liz Allan - 25 Jun, 2026 - Comments: 0

Key Takeaways: A designer’s choice of I/O connectors and interconnect protocols can be the difference between a massively profitable AI chip and a flop. I/O tradeoffs impact airflow, cooling, rack design, power coming into the rack, and other critical aspects of HPC chip design. Reliability is paramount, so standards must be followed, and I/Os need redundant pins. Other innovations... » read more

Verification Methodologies Struggle To Keep Up With AI
By Brian Bailey - 25 Jun, 2026 - Comments: 0

Key Takeaways:  The rapid development of AI has resulted in new capabilities being provided to verification teams, beyond their ability to rationally insert them into accepted methodologies.  There is a lot of uncertainty about who will benefit the most from this technology. Is AI a junior engineer replacement or an enhancer?  The biggest benefits will come when AI helps engineers... » read more

Executive Outlook: Agentic AI’s Impact On Chip Design
By Ed Sperling - 25 Jun, 2026 - Comments: 0

Key Takeaways: Agentic AI has the potential to make engineers more productive, speed time to market, and automate some of the drudge work. The big challenge for design and verification engineers is where and whether they trust AI to get everything right, because there is no margin for error in semiconductors. Having humans in the loop will likely be the rule rather than the exception... » read more

How Far Left Can We Really Shift Verification?
By Frank Schirrmeister - 25 Jun, 2026 - Comments: 0

"Shift left" has been in the engineering lexicon for so long that it risks becoming wallpaper. We nod at it, we put it on slides, and we move on. But the goalposts keep moving. Things that used to live comfortably at the tail end of the design flow — software bring-up, power and performance characterization, thermal analysis — are being dragged earlier and earlier into the schedule, driven ... » read more

Realizing The Future Of 3D-IC Design
By Keith Felton - 25 Jun, 2026 - Comments: 0

The integration of heterogeneous chiplet technology has fundamentally transformed semiconductor design, enabling the efficient creation of sophisticated system-in-packages by assembling pre-designed or third-party IP onto high-performance interposers and advanced packages. This approach offers significant advantages over traditional monolithic designs, including enhanced performance, improved p... » read more

Reducing Avoidable Memory Trips In HBM Systems
By André Bonnardot - 25 Jun, 2026 - Comments: 0

Picture a highway during rush hour. When a road has limited capacity, traffic backs up quickly because only so many cars can move through at once. Adding more lanes increases capacity, but it does not always guarantee a smoother commute. If cars keep flooding onto the highway, if exits are poorly placed, or if drivers have to stay on the road for long distances, congestion can still build. More... » read more

Wafer-Scale vs. Chiplets: The New War? Part 2
By Nandan Nayampally - 25 Jun, 2026 - Comments: 0

In Part 1, we looked at the innovations underpinning the Cerebras WSE-3 and why its most significant breakthrough is the elimination of data movement overhead at the architectural level, not better yield management or thermal engineering. Cerebras’ on-wafer fabric is a viable answer to the question being asked by the entire industry: how do you move data fast enough that compute stops wait... » read more

More Massive Still: Why AI Infrastructure Demands A Unified Design Approach
By Antti Lautanen - 25 Jun, 2026 - Comments: 0

At the recent Data Center World 2026 in Washington, D.C., one message came through louder than ever: AI infrastructure is scaling faster than any system we’ve built before—and the industry can no longer afford to design it in silos. The workshop: “More Massive Still! Delivering AI-Driven Scale in the Face of Historic Constraints” captured this perfectly: the industry is shifting fr... » read more

Introducing An Agentic LLM For Chip Design
By Tanay Biradar - 25 Jun, 2026 - Comments: 0

By Tanay Biradar, Surya Gunukula, Tengxiao Liu, and Kexun Zhang ChipAgents has introduced Renoir, an agentic large language model (LLM) whose name means "renew." In early chip design benchmarks, Renoir outperforms the base model it was trained on and cuts costs by more than half. Furthermore, it can run entirely on-premises, allowing semiconductor companies to develop faster without compromi... » read more

Scaling Production Test Without Scaling Complexity
By Kwan Wee Lee - 25 Jun, 2026 - Comments: 0

Production test teams often need to balance two competing priorities: improving throughput while keeping test development practical and maintainable. As product volumes increase, parallel testing becomes an attractive option because it allows multiple devices under test (DUTs) to run at the same time. In practice, however, multi-DUT execution can introduce duplicated test logic, instrument cont... » read more

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