Low Power-High Performance

Top Stories

Can AI Create Missing Models?
It depends on what those models are used, which also can have a big impact on the cost.
Published on June 11th, 2026 by Brian Bailey

PCIe Benefits From AI, Despite Scaling Protocols
CXL is also gaining traction in AI processing, while MIPI and others are growing at the edge.
Published on June 10th, 2026 by Bryon Moyer

Chiplets Need A New Workflow
Multi-die assemblies are facing full system-level challenges, but engineering teams need coordinated and repeatable ways to identify risks early an...
Published on May 14th, 2026 by Ann Mutschler

Gates Add Functionality, But Wires Create Problems
Wires are treated as a lesser concern, but their neglect is becoming critical at advanced nodes.
Published on May 14th, 2026 by Brian Bailey

Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Published on April 23rd, 2026 by Ann Mutschler

DRAM’s Whac‑A‑Mole Security Crisis
New refresh commands chase Rowhammer and Rowpress, but a permanent fix remains years away.
Published on April 9th, 2026 by Bryon Moyer

A New Era For Co-Processing
Processor architectures are evolving faster than ever, but they still lag the pace of AI development. Chip architects must predict what will be req...
Published on April 9th, 2026 by Brian Bailey

Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
Why latency guarantees, memory movement, power budgets, and rapid model deployment now matter more than raw TOPS.
Published on April 9th, 2026 by Ann Mutschler

CPO Is Extending The Limits Of What’s Possible In A...
Co-packaged optics technology will have a big impact on system power and the cost of data movement.
Published on March 12th, 2026 by Ann Mutschler

AI Power on the Edge
Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It's a hardware/softwa...
Published on March 12th, 2026 by Brian Bailey

More Top Stories »



Round Tables

Can Edge AI Keep Up?
As models evolve faster than silicon cycles, experts weigh how much adaptability architects can afford without sacrificing power, area, or efficiency.
Published on April 23rd, 2026 by Ann Mutschler

Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
Why latency guarantees, memory movement, power budgets, and rapid model deployment now matter more than raw TOPS.
Published on April 9th, 2026 by Ann Mutschler

Balancing Training, Quantization, And Hardware Integratio...
Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.
Published on January 26th, 2026 by Ann Mutschler

Addressing Critical Tradeoffs In NPU Design
Flexibility, future-proofing, and performance considerations for neural processing units.
Published on January 21st, 2026 by Ann Mutschler

How And Why To Optimize NPUs
PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.
Published on January 15th, 2026 by Ann Mutschler

More Roundtables »



Multimedia

New USB Standards: Benefits And Incompatibilities
A roadmap for integrating different versions of the USB and eUSB.
Published on June 23rd, 2026 by Ed Sperling

1 Megawatt Racks In Data Centers
A look inside the next-generation AI server rack.
Published on June 3rd, 2026 by Ed Sperling

New CPU Memory Module
Benefits and questions surrounding a next-gen low-power standard for high-performance compute.
Published on April 28th, 2026 by Ed Sperling

Why More CPUs Are Needed For Agentic AI
General-purpose processing demands will multiply once machines are talking to machines.
Published on April 15th, 2026 by Ed Sperling

State Of The Market For Edge Silicon
What makes one AI chip better than another?
Published on April 8th, 2026 by Ed Sperling

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

IP And LP In SoCs

Cloud HPC For AI: Addressing Latency, Cost, And Scale At ...
Low-latency fabrics, topology-aware scheduling, and tiered memory bring compu...
June 22, 2026
by Sumit Vishwakarma
Best Of Both: LP & HP

Mastering 3D-IC Verification Complexity
Multiphysics analysis for advanced packaging.
June 11, 2026
by Matt Grange
A Bit About Memory

Clocked DDR5 Client Memory Modules Enable Scaling To 9600...
Reliable performance at higher data rates requires tight coordination between...
June 11, 2026
by Carlos Weissenberg
Inside Edge AI Processing

How To Start Building Edge-Native AI
Packet-based architecture enables out-of-order execution to optimize hardware...
June 11, 2026
by Sharad Chole
Co-Packaged Optics Insights

Building A Production-Ready Optically Connected Rack For ...
Delivering the bandwidth density and efficiency needed to scale AI compute cl...
June 11, 2026
by Nandita Aggarwal
Everything Low Power

DDR5 MRDIMM: A Transformational Evolution For DDR5 DIMM
A new architecture enables higher data rates and densities while remaining pi...
June 11, 2026
by Shyam Sharma
At The Core

Beyond The Demo: Deploying And Evaluating Open-Source AI ...
Turn model experimentation into concrete observation of edge AI workloads acr...
June 11, 2026
by Odin Shen
Embedded ML Design

Vision-Language-Action Models Arrive
An emerging AI architecture for embedded autonomy challenges edge efficiency.
May 14, 2026
by Mike Leonard
MIPI And Beyond

Exploring The Latest Innovations In MIPI D-PHY And MIPI C...
Enhanced performance and flexibility for the next generation of high-speed ...
January 15, 2026
by Michael Nagib

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

The Sub-2nm Paradox
Reducing variation in manufacturing, monitoring behavior over time, and targeting specific workloads can have a big impact on power, performance, and area/cost.
by Ed Sperling

Chip Industry Week In Review
AI panel-level packaging innovations at ECTC; cool HBM; 2nm EDA tools; side-channel attacks in 2.5/3D; Huawei claims; IC talent initiative; glass core substrates; memory test facility; Taiwan investments; SiC teamup; DRAM sizing; sequentially stacking silicon; MIPI A-PHY SerDes automotive compliance.
by The SE Staff

Chip Industry Week In Review
Computex shows AI ecosystem; fully autonomous chip design; Intel targets AI racks; Nikon's 1.5 micron L/S litho; IC market rises; Apple's chiplet era; 4,500 chips per AI server rack; HBM price hikes; quantum IPO, chip and roadmap; SiC guidelines; MXenes; EV outlook; autonomous edge chiplets.
by The SE Staff

Toward Agentic Verification
Using AI agents for verifying designs holds huge potential, but can it deliver? And what comes next?
by Brian Bailey

Swapping Out Chiplets: I/Os Vs. Compute
Multi-die assemblies give chip architects the option to change some dies while keeping the rest of the system intact, but which is best to keep?
by Liz Allan

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