category: Top Stories

category: Auto, Security & Edge AI

Can AI Create Missing Models?
By Brian Bailey - 11 Jun, 2026 - Comments: 0

Key takeaways Models are an essential part of EDA flows, each capturing necessary detail while retaining good execution performance. Models have been expensive to create, maintain and verify, restricting their utilization, but AI may be able to significantly reduce their cost. A deeper question remains. Should AI be used to create models that help existing flows, or should AI be used... » read more

PCIe Benefits From AI, Despite Scaling Protocols
By Bryon Moyer - 10 Jun, 2026 - Comments: 0

Key takeaways: PCIe remains a critical technology for non-AI processing. For AI, PCIe will be strengthened by scale-out, agentic AI, and even some scale-up. CXL is seeing uptake, and some even think it could participate in AI processing. PCIe has been the go-to network for most data traffic moving from a processor to devices located elsewhere, which is also what the new data... » read more

Chiplets Need A New Workflow
By Ann Mutschler - 14 May, 2026 - Comments: 0

Key Takeaways: Chiplet design turns semiconductor development into a system-level problem, requiring coordinated workflows across design, packaging, verification, test, and reliability. Successful chiplet workflows must handle multi-physics challenges — especially thermal, mechanical, power, and signal integrity — early enough to reduce costly failures before assembly and tape-out. ... » read more

Gates Add Functionality, But Wires Create Problems
By Brian Bailey - 14 May, 2026 - Comments: 0

Key takeaways: While transistors see continuous improvement, wires keep getting worse because of the smaller geometries and larger chip sizes. There are limited ways to avoid such problems, but the biggest impact will come from floorplanning. Analysis today is not adequate. New developments, such as backside power and 3D integration, provide temporary relief but new materials are a d... » read more

Can Edge AI Keep Up?
By Ann Mutschler - 23 Apr, 2026 - Comments: 0

Key Takeaways: Model development is outpacing silicon design cycles, so edge AI architectures must prioritize adaptability. The required cadence for model updates is highly application-dependent and is closely tied to product lifetime and operational risk. Adaptability can conflict with power, performance, and area targets, so effective heterogeneous architectures and robust softwa... » read more

DRAM’s Whac‑A‑Mole Security Crisis
By Bryon Moyer - 09 Apr, 2026 - Comments: 0

Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

A New Era For Co-Processing
By Brian Bailey - 09 Apr, 2026 - Comments: 0

Key Takeaways: There is no single processor capable of executing everything efficiently, meaning that multiple processors are required. Maximum efficiency is gained by minimizing the movement of data. Architects must maximize efficiency for today's workloads, while also adding enough flexibility to handle tomorrow's. New processor architectures are rapidly evolving thanks to... » read more

Fast Isn’t Fast Enough: Redefining Metrics for Edge AI
By Ann Mutschler - 09 Apr, 2026 - Comments: 0

Key Takeaways: Edge AI performance is about low latency and power efficiency, not peak TOPS. Memory bandwidth and data movement now limit edge AI more than compute. Successful edge AI requires balanced hardware, software, and fast model updates. Experts At The Table: Today’s chip architect must contend with multiple factors when architecting AI processors for fast and effi... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers
By Ann Mutschler - 12 Mar, 2026 - Comments: 0

Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

AI Power on the Edge
By Brian Bailey - 12 Mar, 2026 - Comments: 0

Key takeaways Power and thermal become primary design considerations, not just optimizations. Hardware architectures need to be developed from the ground up. Hardware/software/model co-development is essential. Implementing AI on the edge is driven by a different set of metrics than training or even inference in the cloud. It makes power a first-class citizen, if not the mos... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy