Mask Economics Shape High-NA EUV Adoption


Key Takeaways: Mask costs are not stopping leading-edge scaling, but they increasingly influence design, node, and process choices. High-NA EUV will tighten requirements for CD, EPE, local CDU, mask 3D modeling, stitching, and materials. Reduced depth of focus in High-NA EUV will drive new resist, etch, film, and absorber approaches. Experts at the table: Semiconductor Engin... » read more

How To Build Billions of Bumps


Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

GaN Power Devices Go Vertical


Key Takeaways: On paper, GaN is an excellent candidate for high-voltage power applications. That potential has been difficult to realize due to the lack of sufficiently high-quality starting material. In particular, high-voltage applications require vertical designs. Recent advances in GaN growth are making these designs more feasible. Promising designs and complete process flows hav... » read more

GaN Power Devices Power Up


Key Takeaways: GaN devices are gaining traction due to their ability to tolerate higher voltages. New approaches such as chiplets offer faster switching with less loss. The first applications to benefit from GaN will be low-voltage consumer devices; industrial applications require more work. As electrical power displaces fossil fuels in more applications, system designers ne... » read more

Curvilinear Masks Push The Limits Of Inspection And Metrology


Key Takeaways: Curvilinear masks require native data flows across design, mask data prep, writing, inspection, and metrology. Inspection is shifting from finding all defects to identifying which mask variations actually print on wafer. High-NA EUV will intensify inspection challenges, particularly for small printable defects and actinic contrast limits. Experts at the table... » read more

With Chiplets, What Role Does Economics Play?


Key Takeaways: For the data center, chiplet economics matter, but they’re not a primary decision-driver. With the exception of processor families, chiplets cannot address consumer markets today, where economics dominate. If a chiplet marketplace materializes, the economics may be friendlier because chiplets will have multiple customers and applications. Chiplets are notori... » read more

Low-Temp Solders Are Suddenly Critical For Chiplets And Photonics


Key Takeaways: Tin-bismuth-based solders enable reduced warpage and compatibility with silicon photonics and other temperature-sensitive components. A novel soldering process using white light could help prevent cracks in flip-chip BGA package solder balls, while reducing the carbon footprint. Hypoeutectic Sn-Bi based solders prove especially promising as an SAC305 replacement. ... » read more

Mask Technology Faces A New Set Of Challenges


Key Takeaways: Mask inspection and repair remain the critical bottleneck, even as multi-beam writers have reduced mask-writing constraints. Curvilinear masks are becoming viable for critical layers, but qualification, metrology, and inspection standards still lag production needs. Scaling curvilinear requires curvilinear-native data flows, model-based checks, GPU/HPC compute, and les... » read more

When Semiconductor Materials Misbehave


Key Takeaways Material behavior in production depends on the process context that no development environment can fully replicate. In advanced packaging, the interactions that cross domain boundaries are increasingly where failures originate. The most accurate materials data is also the most commercially sensitive, leaving simulation models calibrated against generic inputs rather tha... » read more

Chiplet Standards Aim For Plug-n-Play


Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

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