Will Your Chip’s Memory Work As Expected?


Increased density at advanced nodes, multi-die assemblies, and the rollout of AI everywhere are making it much more challenging to ensure that memory will function properly over its expected lifetime. Test is no longer about a single memory or one approach for testing memory. It can vary by application, by workload, and by architecture. Some testing is close to memory, some is built into memory... » read more

AI Models Transform Defect Inspection And Review, But Can Fail To Scale


Key Takeaways: AI plays a role in improving defect capture rate and distinguishing between yield-killing and nuisance defects. New developments in wafer edge inspection are proving essential to bonded wafer yields. 70% of AI initiatives stall after pilot implementation, but some pitfalls can be avoided. One of the brightest spots in AI use today is the industry’s ability t... » read more

What I Learned At The 2026 GSA Tech Summit: The Future Of Semiconductor Collaboration Is Full Stack


I had the privilege of joining a panel at the Global Semiconductor Alliance (GSA) Tech Summit in June in Scottsdale, Arizona, titled "Collaboration Models That Actually Work." It was a fitting title for an event that brought together executives from across the semiconductor ecosystem, including foundries, fabless companies, equipment makers, EDA vendors, cloud providers, and systems integrat... » read more

Effective UX/UI Is A Critical Link Between AI Insights And Yield Improvement


The semiconductor industry is undergoing a fundamental shift in how data is generated, analyzed, and acted upon thanks to the integration of AI into process control flows. As AI becomes more deeply integrated into the manufacturing process, its value is increasingly determined not by data-driven decision making alone, but by how effectively its outputs are delivered, interpreted, and acted upon... » read more

High-Speed Manufacturing And In-Field Scan Test Access Via PCI Express For GPIO Limited SoCs


By Ash Patel and Shubharthi Datta, Synopsys, and Chuanyun Fan, Cisco Today’s huge, deep submicron system on chip (SoC) designs present many challenges at every stage of development, from architectural exploration to volume production. This post addresses the specific hurdle of effective and efficient manufacturing tests for these complex devices. It outlines a commercially available soluti... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test


Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp


Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

Enhancing High Bandwidth Memory (HBM) Reliability With 3D X-ray Inspection


High Bandwidth Memory (HBM) is revolutionizing AI, high-performance computing, and advanced graphics systems. Its 3D architecture—stacked DRAM dies interconnected via through-silicon vias (TSVs)—delivers exceptional bandwidth and efficiency. But this complexity introduces new challenges for inspection and quality assurance. Why 3D X-ray for HBM? Traditional 2D X-ray imaging cannot fully v... » read more

Test Anything, Anywhere, Anytime


The semiconductor industry is under relentless pressure to deliver devices that are not only high-performing but also exceptionally reliable across their entire lifecycle. From the moment a chip is tested at the wafer to its deployment in complex systems such as data centers and automotive platforms, the expectation is clear: zero-defect quality at shipment and continuous reliability in the fie... » read more

Advancements in Corona Noncontact Metrology Tools, CnCV, for Industrial WBG Wafer Testing and Electrical Defect Related Yield Prediction


In this review we discuss two recent CnCV metrology advancements, namely: 1. enhancement of throughput and 2. use of electrical defect mapping for yield prediction. Novel 10x faster measurements of critical WBG semiconductor electrical parameters are based on the discovery of a linear UV radiation induced electrical charge biasing.  Example results for an AlGaN/GaN HEMT structure illus... » read more

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